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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8183/ad8185 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 380 mhz, 25 ma, triple 2:1 multiplexers features fully buffered inputs and outputs fast channel-to-channel switching: 15 ns high speed 380 mhz bandwidth (C3 db) 200 mv p-p 310 mhz bandwidth (C3 db) 2 v p-p 1000 v/ m s slew rate g = +1, 2 v step 1150 v/ m s slew rate g = +2, 2 v step fast settling time of 15 ns to 0.1% low power: 25 ma excellent video specifications (r l = 150 v ) gain flatness of 0.1 db to 90 mhz 0.01% differential gain error 0.02 8 differential phase error low all-hostile crosstalk C84 db @ 5 mhz C54 db @ 50 mhz low channe l-to-channel crosstalk C56 db @ 100 mhz high off isolation of C100 db @ 10 mhz low cost fast high impedance output disable feature for connecting multiple devices applications pixel switching for picture-in-picture switching rgb in lcd and plasma displays rgb video switchers and routers product description the ad8183 (g = +1) and ad8185 (g = +2) are high speed triple 2:1 multiplexers. they offer C3 db signal bandwidth up to 380 mhz, along with slew rate of 1000 v/ m s. with better than C90 db of channel-to-channel crosstalk and isolation at 10 mhz, they are useful in many high-speed applications. the differential gain and differential phase errors of 0.01% and 0.02 respectively, along with 0.1 db flatness to 90 mhz make the ad8183 and ad8185 ideal for professional video and rgb multiplexing. they offer 15 ns channel-to-channel switching time, m aking them an excellent choice for switching video signals, while consuming less than 25 ma on 5 v supply voltages. both devices offer a high speed disable feature that can set the output into a high impedance state. this allows the building of larger input arrays while minimizing off channel output loading. they operate on voltage supplies of 5 v and are offered in a 24-lead tssop package. table i. truth table sel a /b oe out 0 0 ina 1 0 inb 0 1 high z 1 1 high z 200mv 2ns v o = 1.4v step r l = 150v 1.4v 1.2v 1.0v 0.8v 0.6v 0.4v 0.2v 0.0v figure 1. ad8185 pulse response; r l = 150 w functional block diagram ad8183/ad8185 in0b gnd in1b gnd in2b in0a dgnd in1a gnd v ee v cc in2a 1 2 3 4 5 6 7 8 9 10 11 12 v cc dvcc v ee out2 v cc v cc oe sel a /b v cc out1 v ee out0 24 23 22 21 20 19 18 17 16 15 14 13 select disable 0 1 2
rev. 0 e2e ad8183/ad8185especifications (t a = 25 8 c, v s = 6 5 v, r l = 1 k v unless otherwise noted) parameter condition min typ max unit dynamic performance e3 db bandwidth (small signal) v out = 200 mv p-p 250/300 590/360 mhz e3 db bandwidth (small signal) v out = 200 mv p-p, r l = 150 w 200/250 380/320 mhz e3 db bandwidth (large signal) v out = 2 v p-p 250/300 530/350 mhz e3 db bandwidth (large si v out = 2 v p-p, r l = 150 w 200/250 310/300 mhz 0.1 db bandwidth v out = 200 mv p-p 90/60 mhz v out = 200 mv p-p, r l = 150 w 100/160 mhz slew rate 2 v step 1000/1150 v/ m s settling time to 0.1% 2 v step, r l = 150 w 15 ns noise/distortion performance differential gain ntsc or pal, 150 w 0.01 % differential phase ntsc or pal, 150 w 0.02 degrees all-hostile crosstalk, rti ? = 5 mhz, ad8185: r l = 150 w e84/e72 db ? = 50 mhz, ad8185: r l = 150 w e54/e50 db channel-to-channel crosstalk, rti ? = 100 mhz, ad8185: r l = 150 w e56/e54 db off isolation ? = 10 mhz, r l = 150 w e100 db voltage noise, rti ? = 10 khz to 30 mhz 28/15 nv/ ? hz dc performance voltage gain error no load 0.20 0.25/0.85 % input offset voltage, rti 5 25/40 mv t min to t max 10 mv input offset voltage matching, rti channel-to-channel 1 25/40 mv input offset drift, rti 15 m v/ c input bias current 6/10 10/15 m a input characteristics input resistance 4/1 8/5 m w input capacitance channel enabled 1 pf channel disabled 1.5 pf input voltage range 3.0/ 1.5 v output characteristics output voltage swing r l = 1 k w 2.90 3.25 v r l = 150 w 2.65 2.95 v short circuit current 60 ma output resistance enabled 0.3 w disabled 4/1 8/3 m w output capacitance disabled 4/6.5 pf power supply operating range 4.5 5.5 v power supply rejection ratio +psrr +v s = +4.5 v to +5.5 v, ev s = e5 v 58/62 66/72 db power supply rejection ratio epsrr ev s = e4.5 v to e5.5 v, +v s = +5 v 52/60 56/68 db quiescent current all channels on 25 30 ma all channels off 3/7 5/10 ma t min to t max ; all channels on 25 ma switching characteristics switch time channel-to-channel 50% logic to 50% output settling in0 = +1 v, in1 = e1 v 15 ns enable to channel on time 50% logic to 50% output settling i nput = 1 v 20 ns enable to channel off time 50% logic to 50% output settling i nput = 1 v 45 ns channel switching transient (glitch) all inputs grounded 50/70 mv digital inputs logic 1 voltage sel a /b and oe inputs 2.0 v logic 0 voltage sel a /b and oe inputs 0.8 v logic 1 input current sel a /b and oe = 4 v 10 na logic 0 input current sel a /b and oe = 0.4 v 0.5 m a operating temperature range temperature range operating (still air) e40 +85 c q ja operating (still air) 128 c/w q jc operating 42 c/w specifications subject to change without notice.
rev. 0 ad8183/ad8185 e3e absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 v dvcc to v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 v internal power dissipation 2, 3 ad8183/ad8185 24-lead tssop (ru) . . . . . . . . . . . . . 1 w input voltage in0a, in0b, in1a, in1b, in2a, in2b . . . . . v ee v in v cc select a /b, oe . . . . . . . . . . . . . . . . . . dgnd v in v cc output short circuit duration . . . . . . . . . . . . . . . . . . . indefinite 3 storage temperature range . . . . . . . . . . . . . . . e65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air (t a = 25 c). 3 24-lead plastic tssop; q ja = 128 c/w. maximum internal power dissipation (p d ) should be derated for ambient temperature (t a ) such that p d < (150 cet a )/ q ja . ordering guide temperature package package model range description option ad8183aru e40 c to +85 c 24-lead plastic tssop ru-24 ad8185aru e40 c to +85 c 24-lead plastic tssop ru-24 ad8183-eval evaluation board ad8185-eval evaluation board maximum power dissipation the maximum power that can be safely dissipated by the ad8183/ ad8185 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determ ined by the glass tran sition tempe rature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the ad 8183/ad8185 is internally short circuit pr otected, this may not be sufficient to guarantee that the maximum junction temperature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 2. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8183/ad8185 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ambient temperature e 8 c 2.0 e50 maximum power dissipation e watts e40 e30 e20 e10 0 10 20 30 40 50 60 70 80 90 1.5 1.0 0 t j = 150 8 c 0.5 figure 2. maximum power dissipation vs. temperature pin configuration top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad8183/ ad8185 in0a v cc dgnd oe in1a sel a /b gnd v cc in2a out0 v cc v ee v ee out1 in2b v cc gnd out2 in1b v ee gnd dvcc in0b v cc
rev. 0 ad8183/ad8185 e4e frequency e mhz 1 0.1 gain e db 0 e1 e2 e3 e4 e5 e6 e7 e8 e9 1 10 100 1k gain flatness v o as shown r l = 150 v 200mv p-p 2v p-p 200mv p-p 2v p-p 0.1 0 e0.1 e0.2 e0.3 e0.4 e0.5 e0.6 flatness e db figure 3. ad8183 frequency response; r l = 150 w frequency e mhz 1 0.1 gain e db 0 e1 e2 e3 e4 e5 e6 e7 e8 e9 1 10 100 1k gain flatness v o as shown r l = 1k v 200mv p-p 2v p-p 200mv p-p 2v p-p 0.1 0 e0.1 e0.2 e0.3 e0.4 e0.5 e0.6 flatness e db 0.2 0.3 figure 4. ad8183 frequency response; r l = 1 k w frequency e mhz 5 0.1 gain e db 4 3 2 1 0 e1 e2 e3 e4 e5 1 10 100 1k v o = 200mv p-p r l = 1k v c l = 5pf temperature as shown +85 c +25 c e40 c figure 5. ad8183 frequency response vs. temperature frequency e mhz 1 0.1 normalized gain e db 0 e1 e2 e3 e4 e5 e6 e7 e8 e9 1 10 100 1k gain flatness v o as shown r l = 150 v 200mv p-p 2v p-p 200mv p-p 2v p-p 0.1 0 e0.1 e0.2 e0.3 e0.4 e0.5 e0.6 normalized flatness e db figure 6. ad8185 frequency response; r l = 150 w frequency e mhz 2 0.1 normalized gain e db 1 0 e1 e2 e3 e4 e5 e6 e7 e8 1 10 100 1k gain flatness v o as shown r l = 1k v 200mv p-p 2v p-p 200mv p-p 2v p-p 0.1 0 e0.1 e0.2 e0.3 e0.4 e0.5 e0.6 normalized flatness e db 0.2 0.3 figure 7. ad8185 frequency response; r l = 1 k w frequency e mhz 4 0.1 normalized gain e db 3 2 1 0 e1 e2 e3 e4 e5 e6 1 10 100 1k v o = 200mv p-p r l = 150 v c l = 5pf temperature as shown +85 c +25 c e40 c figure 8. ad8185 fr equency response vs. temperature
rev. 0 ad8183/ad8185 e5e frequency e mhz e10 1 crosstalk e db e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 10 100 1k r l = 1k v r t = 37.5 v all-hostile adjacent figure 9. ad8183 crosstalk vs. frequency frequency e mhz e10 1 channel-to-channelcrosstalk e db e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 10 100 1k r l = 1k v r t = 37.5 v drive b, listen a drive a, listen b figure 10. ad8183 channel-to-channel crosstalk vs. frequency fundamental frequency e mhz 0 1 distortion e dbc e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 10 100 v o = 2v p-p r l = 150 v second harmonic third harmonic figure 11. ad8183 distortion vs. frequency frequency e mhz e10 1 crosstalk e db e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 10 100 1k r l = 150 v r t = 37.5 v rti measured all-hostile adjacent figure 12. ad8185 crosstalk vs. frequency frequency e mhz e10 1 channel-to-channel crosstalk e db e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 10 100 1k r l = 150 v r t = 37.5 v rti measured drive a, listen b drive b, listen a figure 13. ad8185 channel-to-channel crosstalk vs. frequency fundamental frequency e mhz 0 1 distortion e dbc e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 10 100 v o = 2v p-p r l = 150 v second harmonic third harmonic figure 14. ad8185 distortion vs. frequency
rev. 0 ad8183/ad8185 e6e frequency e mhz 0.1 input impedance e v 1m 100k 10k 1k 100 1 10 100 1k 0 figure 15. ad8183 input impedance vs. frequency frequency e mhz 0.1 output impedance e v 1k 100 10 1 0.1 1 10 100 1k figure 16. ad8183 output impedance vs. frequency; enabled frequency e mhz 0.1 output impedance e v 1m 100k 10k 1k 100 1 10 100 1k 10 figure 17. ad8183 output impedance, vs. frequency; disabled frequency e mhz 0.1 input impedance e v 1m 100k 10k 1k 100 1 10 100 1k 1m figure 18. ad8185 input impedance vs. frequency frequency e mhz 0.1 output impedance e v 1k 100 10 1 0.1 1 10 100 1k 1k figure 19. ad8185 output impedance vs. frequency; enabled frequency e mhz 0.1 output impedance e v 1m 100k 10k 1k 100 1 10 100 1k 10 figure 20. ad8185 output impedance vs. frequency; disabled
rev. 0 ad8183/ad8185 e7e frequency e mhz e40 0.1 off isolation e db e50 e60 e70 e80 e90 e100 e110 e120 e130 e140 1 10 100 500 figure 21. ad8183 off isolation, inputeoutput frequency e mhz e10 0.1 psrr e db 0 10 20 30 40 50 60 70 80 1 10 100 epsrr +psrr figure 22. ad8183 psrr vs. frequency frequency e hz 170 10 voltage noise e nv/ hz 1k 10k 100k 1m 10m 150 130 110 90 70 50 30 10 100 figure 23. ad8183 voltage noise vs. frequency frequency e mhz e40 0.1 off isolation e db e50 e60 e70 e80 e90 e100 e110 e120 e130 e140 1 10 100 500 figure 24. ad8185 off isolation, inputeoutput frequency e mhz e10 0.1 psrr e db 0 10 20 30 40 50 60 70 80 1 10 100 +psrr epsrr figure 25. ad8185 psrr vs. frequency 10 1k 10k 100k 1m 10m 100 frequency e hz 170 voltage noise e nv/ hz 150 130 110 90 70 50 30 10 figure 26. ad8185 rti voltage noise vs. frequency
rev. 0 ad8183/ad8185 e8e v o = 2v step r l = 150 v 0.1%/div 0 5 10 15 20 25 30 35 40 5ns/div figure 27. ad8183 0.1% settling time 10ns sel a /b in0a at +1v in0b at e1v v out 100 90 10 0% C1.0v 0v +1.0v +1.0v +1.8v figure 28. ad8183 channel-to-channel switching time 10ns 100 90 10 0% sel a /b C0.05v 0v +0.05v +1.0v +1.8v figure 29. ad8183 channel-to-channel switching transient (glitch) v o = 2v step r l = 150 v 0.1%/div 0 5 10 15 20 25 30 35 40 5ns/div figure 30. ad8185 0.1% settling time 10ns 100 90 10 0% sel a /b in0a at +0.5v in0b at C0.5v v out C1.0v 0v +1.0v +1.0v +1.8v figure 31. ad8185 channel-to-channel switching time 10ns sel a /b 100 90 10 0% C0.05v 0v +0.05v +1.0v +1.8v figure 32. ad8185 channel-to-channel switching transient (glitch)
rev. 0 ad8183/ad8185 e9e 25mv 2ns v o = 200mv step r l = 1k v 0.10v 0.05v 0.0v e0.05v e0.10v figure 33. ad8183 small signal pulse response; r l = 1 k w 100mv 2ns v o = 0.7v step r l = 1k v 0.7v 0.6v 0.5v 0.4v 0.3v 0.2v 0.1v 0.0v figure 34. ad8183 video amplitude pulse response; r l = 1 k w 250mv 2ns v o = 2v step r l = 1k v 1.0v 0.5v 0.0v e0.5v e1.0v figure 35. ad8183 large signal pulse response; r l = 1 k w 25mv 2ns v o = 200mv step r l = 150 v 0.1v 0.05v 0.0v e0.05v e0.1v figure 36. a d8185 small signal pulse response; r l = 150 w 200mv 2ns v o = 1.4v step r l = 150 v 1.4v 1.0v 0.6v 0.2v 1.2v 0.8v 0.4v 0.0v figure 37. ad8185 video amplitude pulse response; r l = 150 w 250mv 2ns v o = 2v step r l = 150 v 1.0v 0.5v 0.0v e0.5v e1.0v figure 38. ad8185 large signal pulse response; r l = 150 w
rev. 0 ad8183/ad8185 e10e theory of operation the ad8183 (g = +1) and ad8185 (g = +2) are triple-output, 2:1 multiplexers with ttl-compatible global input switching and output enable control. optimized for selecting between two rgb (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. additionally, the multiplexers are compensated for high phase margin, minimizing overshoot for good pixel resolution. the multiplexers also have video specifications that are suitable for switching ntsc or pal composite signals. the multiplexers are organized as three independent channels, each with two input transconductance stages and one output transimpedance stage. the appropriate input transconductance stages are selected via one logic pin (select a /b), such that all three outputs switch input connections simultaneously. the unused input stages are disabled with a t-switch scheme to provide excellent crosstalk isolation between on and off inputs. no additional input buffering is necessary, resulting in low input capacitance and high input impedance without addi- tional signal degradation. the transconductance stages, npn differential pairs, source signal current into the folded cascode output stages. each out- put stage contains a compensating network and emitter follower output buffer. internal voltage feedback sets the gain with the ad8183 being configured as a unity gain follower, and the ad8185 as a gain-of-two amplifier with a feedback network. this architecture provides drive for a reverse-terminated video load (150 w ) with low differential gain and phase error for relatively low power consumption. careful chip design and layout allow excellent crosstalk isolation between channels. one logic pin oe controls whether the three outputs are enabled, or disabled to a high-impedance state. the high impedance disable allows larger matrices to be built when busing the outputs together. also, when not in use the outputs can be disabled to reduce power consumption. in the case of the ad8185 (g = +2), a feedback isolation scheme is used so that the impedance of the gain-of-two feedback network does not load the output. note that full power bandwidth for an undistorted sinusoidal signal is often calculated using peak slew rate from the equation: full power bandwidth peak slew rate sinusoid amplitude = () 2 p peak slew rate is not the same as average slew rate (25% to 75%) as typically specified. for a natural response, peak slew rate may be 2.7 times larger than average slew rate. therefore, calcu- lating a full power bandwidth with a specified average slew rate will give a pessimistic result. applications driving capacitive loads when driv ing a large capacitive load, m ost amplifiers will exhibit peaking/ringing in pulse response. to minimize peaking, and to ensure stability for larger values of capacitive loads, a small resistor, r s , can be added between the output and the load capacitor, c l . this is shown in figure 39. 5ns 0.5v 0.0v e0.5v 250mv r s = 0 v , c l = 5pf r s = 15 v , c l = 20pf r s = 20 v , c l = 20pf c l 1k v v in v out r s 75 v figure 39. pulse responses driving capacitive loads power supply and layout considerations the ad8183 and ad8185 are very high performance muxes that require attention to several important design details to real- ize their specified performance. good high-frequency layout rules must be carefully observed. a good design will start with a solid ground plane. all the gnd pins of the part(s) should be directly connected to it. in addi- tion, bypass capacitors should be connected from each supply pin (v cc and v ee ) to the ground plane. it is suggested to use 0.01 m f surface-mount chip capacitors as close to the ic as possible to provide high-frequency bypassing. for lower frequency bypassing, higher value tantalum capacitors? at least 10 m f?should be provided from both v cc and v ee to ground. these do not have to be as close to the ic pins, because parasitic inductance is not as big a factor at low frequencies. please refer to ad8183/ad8185 evaluation board operation guide for further information. crosstalk in normal operation the ad8183 and ad8185 will have signals at some of the input pins that are not switched to appear at the output. in addition, several signal paths will in general be active at one time. in any system that has high-frequency signals that are brought together in close proximity, there will be inevitable crosstalk, whereby some fraction of the undesired signals will appear at the outputs. this can result, for example, in ghost images in an rgb monitor muxing application. the ad8183 and ad8185 are capable of excellent low- crosstalk performance. however, in order to realize the best possible crosstalk performance, certain design details should be followed. most of the low-crosstalk specification is inherent in the part and will result from observing the power supply and layout consideration discussed above. this is because each of the input and output pins are separated by at least either a supply pin or a ground pin. this package architecture helps the crosstalk performance in at least three ways. first, the supply and ground pins provide extra physical separation between the input- and output-signal pins. physical separation is a very effective technique for reducing crosstalk. second, the supply and ground pins are at ac ground, and there- fore provide a degree of shielding between the signals. this works for both capacitive crosstalk, which is due to voltages on the signals, and inductive crosstalk, which is due to currents that flow through the signal paths.
rev. 0 ad8183/ad8185 e11e third, the additional power and ground pins also yield lower impedance on the power and ground lines, and therefore minimize the effects of shared impedances on crosstalk. signal routing is also important for keeping crosstalk low. shielding and separation should be used for signals that must run parallel over some length on the pc board. if signals must cross, the trace w idths should be kept narrow, and the signals should cross at right angles to minimize the capacitance between the traces. 4:1 rgb multiplexer for selecting among four rgb sources to drive a monitor, two ad8185s can be combined to make a 4:1 rgb multiplexer. a circuit for this is shown in figure 40. each rgb source is con- nected to either the three a or b inputs of one of the ad8185s. in addition, all r signals are tied to 0 inputs, all g signals are tied to 1 inputs, and all b signals are tied to 2 inputs. all of these input signals should be terminated with the standard 75 w to ground very close to the ic pins. each of the outputs of the ad8185 has a series 75 w resistor to provide a back termination for the monitor load. whichever device is selected will drive the output signal through its three termination resistors. when terminated by the monitor, the voltage of these signals will be attenuated by a factor of two. this is normalized by the gain-of-two of the ad8185. unlike many gain-of-two circuits, the impedance of the ad8185 is very high when it is disabled. this is due to a proprietary circuit that disconnects the feedback network from a low imped- ance when the part is disabled. oe oe oe oe oe oe out0 out1 out2 75 v 75 v 75 v blue green red to monitor 75 v 75 v 75 v 75 v 75 v 75 v r g b source 0 r g b source 1 75 v 75 v 75 v 75 v 75 v 75 v r g b source 2 r g b source 3 sel 0 sel 1 oe sel a /b in2b in2a in1b in1a in0b in0a oe sel a /b in2b in2a in1b in1a in0b in0a out0 out1 out2 75 v 75 v 75 v 200 v 100pf 200 v 100pf figure 40. 4:1 rgb multiplexer two control bits are required to select the input source for the rgb signals. one is applied to each of the sel a /b inputs of each device to select between the two input sources for that device. the other bit controls the oe inputs of the two devices. a delay circuit is provided for each device to ensure that the outputs of one device are disabled before the outputs of the other are enabled. if the rgb signals contain the sync information, such as a sync- on-green, this circuit is all that is necessary for the full 4:1 rgb mux. however, if sync is carried on separate signals, such as in pcs, the sync signals can be multiplexed through a digital multi- plexer that operates from the same sel signals. the rc in the oe circuit is to ensure break-before-make operation. using the values shown, a 20 ns time constant is created. this will delay the enabling of the outputs of the new selection until after the other devices? outputs are disabled. this time can be shortened or eliminated if the system can tolerate the glitches caused by simultaneously enabled outputs. evaluation board power and ground there are three power supply pins on the board. v cc is +5 v analog, v ee is e5 v analog, and dvcc is +5 v digital. these three power supply pins should be connected to good quality, low noise supplies. if the same 5 v power supply is used for both analog and digital, separate cables should be run from the power supply to the evaluation board?s an alog and digital power supply pins. three 10 m f tantalum capacitors (c1ec3) are located under the power connector to decouple the power supplies as they first enter the board. as the three supplies get close to the part, they are again decoupled with 0.1 m f ceramic capacitors (c4ec6). finally, each power pin of the device is locally decoupled with a 0.01 m f ceramic capacitor (c7ec15). the board has a separate analog and digital ground plane. with the jumper at w5 installed, these two ground planes are tied together on the board. generally, this jumper should remain installed. inputs and outputs the evaluation board has been carefully laid out to demonstrate the high speed performance of the device. optimized for video applications, all signal inputs are terminated with 75 w resistors to ground (r1er6). the three outputs are backterminated with 75 w series resistors (r12er14). stripline techniques are used to achieve a 75 w characteristic impedance on the input and output lines. see figure 41 for the arrangement of the pcb layers. top layer 75 v signal layer power layer 50 v signal layer 0.005" (127mm) 0.0026" (66mm) 0.0038" (96.5mm) 0.0176" (447mm) 0.028" (711mm) 0.005" (127mm) figure 41. pcb dimensions in addition, 75 w bnc conn ectors are used on the six inputs (j1ej6) and three outputs (j7ej9). the connectors are arranged in a crescent around the device. this results in all the input and output signal traces having the same length. unused regions of the multilayer board are filled up with ground planes. as a
rev. 0 ad8183/ad8185 e12e result, the input and output traces, in addition to having a con- trolled impedance, are well shielded. sel a /b and oe sel a /b (pin 22 of the device) allows the a or b inputs to be selected. when sel a /b is at logic low, (equal to or less than 0.8 v), inputs 0a, 1a and 2a are directed to outputs 0, 1, and 2, respectively. when sel a /b is at logic high, (equal to or greater than 2.0 v), inputs 0b, 1b, and 2b are directed to outputs 0, 1, and 2, respectively. there are two ways to provide sel a /b to the device: using a jumper or a bnc connection. with the jumper in the w4 posi- tion, sel a /b is tied to ground. this selects the a inputs. with the jumper in the w3 position, sel a /b is tied to 5 v, through pull up resistor r15. this selects the b inputs. if faster use of sel a /b is desired, the 50 w bnc connector at j10 can be used. if j10 is used, there must not be a jumper on w3 and w4. microstrip line techniques provide a 50 w charac- teristic impedance from j10 to the device. please refer to figure figure 42. evaluation board schematic 41 for the arrangement of the pcb layers. if j10 is used, the user may wish to install a 50 w termination resistor at r10. oe (pin 23 of the device) allows the three outputs to be enabled or disabled. w hen oe is at logic low, (equal to or less than 0.8 v), outputs 0, 1, and 2 are enabled. when oe is at logic high, (equal to or greater than 2.0 v), outputs 0, 1, and 2 are disabled (placed into a high impedance state). once again, there are two different ways to provide oe to the device: using a jumper or a bnc connection. with the jumper in the w2 position, oe is tied to ground. this enables the outputs. with the jumper in the w1 position, oe is tied to 5 v, through pull-up resistor r16. this selects hi z, or high impedance, and the outputs are disabled. if faster use of oe is desired, the 50 w bnc connector at j11 can be used. if j11 is used, there must not be a jumper on w1 and w2. microstrip line techniques provide a 50 w characteris- tic impedance from j11 to the device. please refer to figure 41 for the arrangement of the pcb layers. if j11 is used, the user may wish to install a 50 w termination resistor at r11. in0a dgnd in1a agnd in2a v cc v ee in2b agnd in1b agnd in0b v cc oe sel a /b v cc out0 v ee out1 v cc out2 v ee dvcc v cc ad8183/ ad8185 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 dgnd agnd agnd agnd c8 0.01 m f agnd c7 0.01 m f agnd v cc v ee 75 v stripline r3 75 v agnd j3 in2a 75 v stripline r2 75 v agnd j2 in1a 75 v stripline r1 75 v agnd j1 in0a 75 v stripline r6 75 v agnd j6 in0b 75 v stripline r5 75 v agnd j5 in1b 75 v stripline r4 75 v agnd j4 in2b w5 agnd dgnd c9 0.01 m f agnd c10 0.01 m f dgnd c11 0.01 m f agnd v ee dvcc v cc c12 0.01 m f agnd v cc c13 0.01 m f agnd v ee c14 0.01 m f agnd v cc r10 50 v dgnd r13 75 v j8 out1 75 v stripline r12 75 v j7 out2 75 v stripline r14 75 v j9 out0 75 v stripline optional 50 v microstrip line dgnd w4 w3 r15 20k v v cc sel a /b j10 c15 0.01 m f agnd v cc r11 50 v dgnd optional 50 v microstrip line dgnd w2 w1 r16 20k v v cc oe j11 oe p1 dvcc 1 c3 10 m f dgnd + dvcc c6 0.1 m f dgnd dvcc p1 dgnd 2 dgnd dgnd p1 v ee 4 c2 10 m f agnd + v ee c5 0.1 m f agnd v ee p1 agnd 5 agnd agnd p1 v cc 6 c1 10 m f agnd + v cc c4 0.1 m f agnd v cc sel a /b dut
rev. 0 ad8183/ad8185 e13e figure 43. component side silkscreen figure 44. board layout (component side)
rev. 0 ad8183/ad8185 e14e figure 45. board layout (75 w signal layer) figure 46. board layout (ground plane)
rev. 0 ad8183/ad8185 e15e figure 47. board layout (circuit side;) 50 w signal layer figure 48. circuit side silkscreen
rev. 0 ad8183/ad8185 e16e outline dimensions dimensions shown in inches and (mm). c3689e5e10/99 printed in u.s.a. 24-lead plastic tssop (ru-24) 24 13 12 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.311 (7.90) 0.303 (7.70) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 8 0 8

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